When a large-sized complementary metal-oxide semiconductor (CMOS) image sensor (CIS) is formed of a single chip, a yield is decreased because of poor obtaining efficiency of a chip from a wafer. Therefore, it is considered to improve productivity of the large-sized CIS by tiling a plurality of small-sized CISs each of which is formed of a single chip and electrically connecting them by wire bonding to manufacture the large-sized CIS (for example, refer to Patent Document 1).
However, there is a large gap (connection) of the order of millimeters due to the wire bonding between the small-sized CISs included in the large-sized CIS manufactured in this manner, and it is not possible to receive the light entering the gap by the small-sized CIS. Therefore, in order to generate one imaged image having a size corresponding to the large-sized CIS, it is required to generate an image corresponding to the light entering the gap by performing image processing such as interpolation by using the image imaged by each of the small-sized CISs, so that there is a large load in image processing. Therefore, it is difficult to generate the imaged image at high resolution and high frame rate having the size corresponding to the large-sized CIS, and such large-sized CIS is not suitable for imaging application.